SoC/IP Design Verification Engineer

About This Role

• We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks.
• You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.
• You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.
• What You'll Do (Key Responsibilities) • Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff. • Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components. • Develop test content: constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions. • Debug failures quickly and methodically across simulation and emulation (waveforms, logs, assertions, checkers, reference model mismatches). • Drive coverage closure (functional and code coverage): define, measure, analyze holes, and implement closure strategies. • Leverage assertions (SVA) and formal where appropriate to strengthen verification quality and accelerate bug find. • Integrate VIPs (e.g., AXI/ACE/PCIe/DDR) and coordinate with external/internal IP teams for models, checkers, and coverage. • Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability. • Continuously improve flows: contribute to methodology, regressions, CI/CD, and verification infrastructure (e.g., Makefiles, Python utilities, farm scripts). • Document plans, environments, and results; present status, risks, and signoff evidence to stakeholders.