Design Verification Engineer

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About This Role

  • The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs.
  • The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements.
  • The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (SystemVerilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using SystemVerilog; and developing random & directed test cases against the specification.
  • This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results.
  • Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.
  • Job Requirements: A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ year’s relevant industry work experience.
  • Experience in verifying designs at system level and block level.
  • Fluent knowledge of RTL verification methodologies including SystemVerilog.
  • Strong experience in ASIC design verification flows and DV methodologies Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
  • Strong and independent design debugging capability.
  • Strong verbal and written communication skills.
  • Must be comfortable working in a team environment with verification team and design team members.
  • Demonstrated ability to analyze and resolve complex verification trade-off scenarios.
  • Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus.
  • Experience working with Emulators and FPGA based prototyping is a plus.
  • Familiarity with overall chip design methodologies and tools Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
  • Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.
  • We will also consider qualified applicants with arrest and conviction records consistent with local law.
  • If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Broadcom

USA-CA San Jose Innovation Drive

Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Broadcom
370 positions
Job ID
/job/USA-CA-San-Jose-Innovation-Drive/Design-Verification-Engineer_R024289

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