HBM/DDR/SERDES DFT Verification Lead Engineer

About This Role

• Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center.
• We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team.
• In this role, you will play a crucial part in ensuring the robustness and reliability of our HBM, DDR and SerDes designs through comprehensive Design for Test (DFT) verification strategies.
• You will work collaboratively with cross-functional teams to develop, implement, and validate DFT methodologies, guaranteeing that our products meet the highest quality standards.
• Key Responsibilities: Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.
• Collaborate with design and architecture teams to identify and define critical testability requirements.
• Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
• Analyze DFT-related data and provide insights for continuous design improvements.
• Document verification processes, results, and best practices to enhance team knowledge and efficiency.
• Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.
• Working closely with STA and DI Engineers design closure for test Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase Assisting with silicon failure analysis, diagnostics & yield improvement efforts Interfacing with the customers, physical design and test engineering/manufacturing teams located globally Working closely with I/P DFT engineers & other stakeholders Debugging customer returned parts on the ATE Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond Automating DFT & Test Vector Generation flows Skills/Experience: Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others) Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.
• Understanding of DFT methodologies, including scan, BIST, and ATPG.
• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).
• Excellent analytical and problem-solving skills.
• Strong communication and teamwork abilities.
• The ability to work in a multi-disciplined, cross-department environment Solid knowledge in analog and digital circuit design, and device physics fundamentals Excellent problem solving, debug , root cause analysis and communication skills Experience working on ATE is a plus Familiarity with BIST logic for array and link testing is a plus Knowledge of AHB/APB/AXI buses is a plus Education & Experience: Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000.
• This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
• Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.