Senior Physical Design Engineer STA

About This Role

• Mission, Team Context The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks.
• The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
• The Role and Impact: As a Physical Design Timing Engineer, you will play a pivotal role in driving the success of Intel's next-generation mixed signal IPs.
• Your work will directly contribute to delivering high-performance, low-power designs that power innovative products and shape the future of technology.
• Leveraging your expertise in timing analysis and optimization, you will be integral in ensuring the efficiency, functionality, and performance of Intel's cutting-edge designs.
• This position offers the opportunity to collaborate with cross-functional teams, influence chip architectures, and develop methodologies that set new industry standards.
• Key Responsibilities: - Perform timing analysis and optimization to meet design specifications at the Partition and IP level levels. - Generate and verify timing constraints, addressing timing violations across complex SoC designs. - Conduct timing rollups, ensuring designs meet functionality, performance, and power goals. - Develop performance and power-optimized clock networks, collaborating with clocking and backend teams. - Define methodologies for high-quality timing models to optimize physical design team efficiency. - Establish process, voltage, and temperature (PVT) conditions for timing analysis based on product requirements. - Work closely with architecture, clocking design, and logic design teams to support flow development, chip integration, and clock network validation. - Drive timing fixes, clocking balance, and power delivery through close coordination with full-chip designers. - Ensure timing budgets are met and collaborate on timing closure reviews.