Senior Physical Design Engineer

About This Role

• The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks.
• The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
• Role Summary The Physical Design Engineer (Grade 7) is a hands-on individual contributor responsible for block-level Physical Design execution of Hard-IPs and Testchips.
• The role requires consistent delivery under defined methodologies, clear ownership of assigned design blocks, and strong execution rigor while building toward broader end-to-end responsibility.
• Key Responsibilities • Own block-level Physical Design from netlist handoff through GDSII under established methodologies. • Execute floorplanning, power intent setup, placement, CTS, routing, optimization, and ECO closure. • Run and debug Physical Design flows using standard tool environments. • Support physical sign-off activities including DRC/LVS and directed IR/EM analysis. • Analyze and improve QoR metrics (timing, power, area) for assigned blocks. • Use and enhance scripting and automation to improve productivity and execution quality. • Partner with Logic, STA, Analog Layout, and Methodology teams to resolve design issues. • Follow SAM-defined execution standards, checklists, and quality gates.