Mixed Signal IP Verification Engineer

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Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.

Candidate must possess a BS, MS degree with 10+ years of relevant industry experience in Design verification, SystemVerilog and OVM/UVM. • Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS • Capable of multitasking in dynamic environment with multiple teams from different geos • Solid verbal and written communication skills • Excellent debug and problem solving skills Preferred Qualifications: • Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols • Good scripting skills in Python/Perl • Exposed to Formal Property Verification and Git version control VSCode GitHub CoPilot or any other AI experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

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