Opens intel.wd1.myworkdayjobs.com in a new tab
About This Role
- The Role and Impact As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of industry-leading technologies by contributing to the development of high-speed, low-power IPs for next-generation products.
- You will work in a dynamic, innovative environment, collaborating with cross-functional teams to deliver robust and efficient mixed signal designs.
- By owning and delivering the logic design of Mixed Signal IPs, you will directly influence Intel's mission to create world-changing technology that enables global progress and enriches lives.
- Key Responsibilities - Define and implement microarchitecture and RTL designs for mixed signal and high-speed IP blocks using SystemVerilog. - Collaborate closely with architecture and system teams to optimize power, performance, and area for IP designs. - Develop and utilize automation flows for IP logic design, ensuring high-quality RTL through tools such as Lint, CDC, and synthesis QA checks. - Conduct power and performance analysis, driving improvements in area and power efficiency across designs. - Review verification plans and resolve RTL issues to ensure feature correctness and design integrity. - Support SoC teams, ensuring seamless integration and high-quality delivery of IP modules. - Innovate and implement automated solutions to streamline coverage closure and timing convergence.
Requirements
- Bachelor's or Master's degree in Electrical or Computer Engineering, or a closely related field. - 4-12 years of experience with a Bachelor's degree or 3-10 years of experience with a Master's degree. - Strong expertise in RTL development using SystemVerilog. - Proficiency in low-power design techniques, including UPF, clock gating, and multiple clock domain design. - Hands-on experience with front-end design tools such as Spyglass, VC Lint, CDC, and synthesis tools. - Solid understanding of state machine design, simulation, and debugging using tools like VCS and Verdi. - Scripting proficiency in Perl, Python, or TCL for design automation and workflow optimization.
- Preferred Qualifications - Familiarity with DFI, DDR, or LPDDR protocols and DDR PHY/Memory Controller designs. - Basic understanding of analog design to facilitate optimal integration of analog and digital components. - Pre-silicon and post-silicon validation experience is an advantage. - Knowledge of area and power optimization techniques for IP designs. - Strong problem-solving skills with the ability to make critical technical decisions in complex situations.
- Join us in redefining the boundaries of technology and innovation.
- Apply today to be part of a team that drives transformative solutions for tomorrow's challenges.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
Opens intel.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
646 positions
Job ID
/job/India-Bangalore/Mixed-Signal-Logic-Design-Engineer_JR0285540
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar RTL Design roles
Marvell Technology
Sr. Principal Engineer, RTL ASIC Design
Hyderabad|RTL Design
Analog Devices
Senior Engineer, Digital Design Engineer
US, MA, Wilmington|RTL Design
NXP Semiconductors
Principal Digital Design Engineer
Bangalore|RTL Design
Marvell Technology
Senior Staff- IP RTL Design Engineer
Bangalore|RTL Design