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What You'll Do
- Design and develop RTL (Register Transfer Level) code using Verilog/SystemVerilog/VHDL Architect and implement complex digital blocks and subsystems Perform functional verification using simulation tools and methodologies (UVM/OVM) Develop and execute testbenches and validation plans Perform logic synthesis , timing analysis, and area optimization Debug and troubleshoot design issues at RTL, gate, and silicon levels Collaborate with verification, physical design, and firmware teams Ensure designs meet power, performance, and area (PPA) targets Participate in design reviews, code reviews, and technical discussions Work with EDA tools for design implementation and validation Support post-silicon validation and bring-up activities Required Skills & Expertise Technical Skills Strong proficiency in: Verilog / SystemVerilog / VHDL Experience with: RTL design and simulation tools (ModelSim, VCS, Xcelium) Synthesis tools (Design Compiler, Genus) Static Timing Analysis (PrimeTime) Understanding of: Digital logic design concepts FSMs, pipelining, clock domain crossing (CDC) Low-power design techniques Knowledge of: FPGA/ASIC design flow Bus protocols (AXI, AHB, APB) Experience in debugging using: Waveform tools (Verdi, SimVision) Preferred Skills Experience with UVM-based verification methodology Familiarity with DFT (Design for Testability) concepts Exposure to scripting languages like Python, Perl, or TCL Knowledge of hardware-software co-design Experience in high-speed interfaces or SoC design Experience Requirements Typically 10+ years of experience in digital design or ASIC/FPGA development Proven track record of successful tape-outs or product deliveries Education Bachelor’s or Master’s degree in: Electronics Engineering Electrical Engineering VLSI Design Computer Engineering Soft Skills Strong problem-solving and debugging abilities Excellent communication and teamwork skills Ability to work in fast-paced, deadline-driven environments Attention to detail and quality-focused mindset More information about NXP in India... #LI-29f4
Tools & Skills
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
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708 positions
Job ID
/job/Bangalore/Principal-Digital-Design-Engineer_R-10064535
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