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About This Role
- The Role and Impact As a Physical Design Timing Engineer, you will play a critical role in delivering Intel's next-generation System-on-Chip (SoC) products.
- In this position, you will focus on ensuring optimal timing, power efficiency, and performance of Intel's cutting-edge designs.
- Your expertise will directly impact Intel's ability to deliver high-performance, power-optimized, and innovative products that redefine the technology landscape.
- Collaborating with cross-functional teams, you will drive the development of advanced methodologies and solutions to tackle complex technical challenges and help shape the future of computing.
- Key Responsibilities - Perform comprehensive timing analysis and optimization to ensure robust, high-performance designs. - Generate and validate timing constraints and address timing violations at the chip and block levels for SoCs. - Conduct timing rollups and ensure functionality of designs with optimized performance and power characteristics. - Develop and implement methodologies to produce high-quality timing models that enhance the efficiency of the physical design team. - Define process, voltage, and temperature (PVT) conditions tailored to product operating plans and binning requirements for precise timing analysis. - Collaborate with clocking teams and full-chip designers to maintain clocking balance, resolve timing issues, and optimize power delivery and partitioning. - Partner with architecture, clocking design, and logic design teams to define and validate advanced SoC clocking flows and methodologies. - Ensure adherence to high-performance, low-power clock network guidelines while driving flow development for seamless chip integration.
Requirements
- Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field and/or prolonged course of study in a specialized area, or equivalent experience per job requirements. - At least 12 years of experience with a Bachelor's degree, 8 years with a Master's degree, or 6 years with a PhD in timing analysis, physical design, or a related domain. - Proficiency in static timing analysis, timing constraint generation, and timing optimization techniques. - Experience with tools, flows, and methodologies (TFM) for physical design and timing analysis. - Strong knowledge of SoC clocking, timing budgeting, and constraint adaptation. - Familiarity with scripting languages such as TCL for automation and design optimization. - Understanding of digital design fundamentals, power and performance analysis, and optimization techniques.
- Preferred Qualifications - Exposure to signal and power integrity analysis and optimization. - Proven ability to collaborate with cross-functional teams, including architecture, logic design, and clocking teams. - Strong problem-solving skills and the ability to work on complex, large-scale designs. - Experience working with advanced process nodes and knowledge of industry-leading EDA tools.
- Join us in pushing the boundaries of technology and making a global impact.
- Be part of a dynamic team where your expertise will contribute to groundbreaking innovations and technological breakthroughs.
- Apply today to be part of Intel's journey to shape the future of the semiconductor industry.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
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Specialisation
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646 positions
Job ID
/job/US-California-Santa-Clara/Director--Silicon-Design-Engineering_JR0284973
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