Design Verification Engineer

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About This Role

  • Lead ASIC Design Verification Engineer We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation silicon.
  • In this role, you will oversee and execute both block-level and system-level verification, ensuring the architectural integrity of complex SoC designs.
  • You will collaborate closely with cross-functional design and verification teams to resolve complex trade-offs and deliver high-quality silicon on advanced node technologies.
  • Key Responsibilities End-to-End Verification: Lead and execute comprehensive verification strategies at both the block and system levels.
  • Methodology Architecture: Define, deploy, and enhance advanced ASIC design verification flows and DV methodologies.
  • Environment Development: Build robust, scalable, object-oriented verification environments and testbenches.
  • Debug & Analysis: Independently debug complex design and verification issues; analyze and resolve intricate verification trade-off scenarios.
  • Cross-Functional Collaboration: Partner closely with design and verification teams to ensure alignment on coverage, timelines, and architectural goals.
  • Required Qualifications Education: Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or a related field.
  • Experience: 12+ years of relevant industry experience in ASIC design verification (preferred).
  • Methodologies: Deep fluency in RTL verification methodologies, including SystemVerilog .
  • Frameworks & Languages: Strong working knowledge of object-oriented verification languages UVM , C/C++ , and scripting languages ( Perl, Python, or Tcl ).
  • Advanced Nodes: Experience working with advanced process node technologies (e.g., 5nm and below ) is highly desired.
  • Soft Skills: Exceptional verbal and written communication skills; proven ability to thrive and lead in a collaborative team environment.
  • Work Authorization: Must have legal authorization to work in the US.
  • Preferred & Bonus Skills Experience with hardware design, hardware debugging, and SystemC or other programming languages.
  • Hands-on experience with hardware emulation (e.g., Palladium, Zebu) and FPGA-based prototyping .
  • Broad familiarity with overall chip design methodologies, EDA tools, and front-to-back silicon development lifecycles.
  • Additional Job Description: Compensation and Benefits The annual base salary range for this position is $143,800 - $230,000 .
  • As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
  • All subject to relevant plan documents and award agreements.
  • Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.
  • We will also consider qualified applicants with arrest and conviction records consistent with local law.
  • If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Broadcom

USA-CA San Jose Innovation Drive

Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Broadcom
339 positions
Job ID
/job/USA-CA-San-Jose-Innovation-Drive/Design-Verification-Engineer_R026294

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