Principal Engineer

About This Role

• Broadcom Limited offers an excellent opportunity to contribute to a team environment and to grow personal career path.
• You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom’s leading-edge CMOS cell-based ASIC technologies.
• You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support.
• Candidates will have opportunity to work on the latest 5nm/3nm designs Detail design tasks include Full Chip Synthesis and STA: An ideal candidate should have some background on full chip synthesis flow (DC, DCT, DCG) for 5nm/3nm design tape out.
• It would be better if the candidate have the experience running full chip STA and constraint clean up flow.
• Physical Design Implementation : An ideal candidate having some background in either the Physical Design which includes floor planning, placement, design closure, and DRC & LVS skills.
• Overall, candidates are expected to develop the most of above skills.
• Candidates who have the desire to seek the in-depth and broad technical challenge should apply.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.