Sr Principal Application Engineer - Design Verification

Overview

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Job Responsibility: 1.
• Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, AI solution, simulation Emulation and Acceleration products.
• Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
• Train, ramp-up and accompany customer project.
• Conduct basic and advanced trainings, presentations and demos as necessary.
• Providing technical expertise to address clients’ queries, which need expert involvement.
• Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
• Job Requirements: 4-6 or above years’ experience in the following areas: 1.
• Design experience in Verilog/VHDL for IP or SoC chip level.
• Verification with knowledge of SystemVerilog/VHDL and HDL simulators.
• Experience of using formal verification, Jasper experience is a plus.
• Experience with hardware emulator or accelerator is a big advantage.
• Experience of advanced verification methodology like UVM is a plus.
• Experience of AI for design and verification is a big advantage.
• Strong verbal and written communication skills in Japanese is needed.
• Business-level English proficiency is preferred.
• Strong teamwork skills with good human relationship.
• We’re doing work that matters.
• Help us solve what others can’t.