STA methodology engineer

What You'll Do

• Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.
• Collaborate with cross-functional teams to validate and refine timing constraints.
• Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.
• Perform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis using Logic Libraries Integration flow checks.
• Contribute to the development and automation of STA flows and methodologies.
• Required Qualifications: Bachelor’s or Master’s degree in Electrical or Electronics Engineering. 10–12 years of hands-on experience in STA, with proven tape-out experience as a block owner or lead.
• Deep understanding of STA concepts, timing constraints, and closure methodologies at both block and SoC levels.
• Proficient in handling timing-related issues such as DRCs, annotation, multivoltage flows, noise, and crosstalk.
• Strong collaboration skills and ability to work across teams to drive methodology improvements.
• Preferred Skills: Proficiency in Python scripting.
• Overview/understanding of AI/GenAI would be added advantage.
• Experience in developing or enhancing STA flow automation.
• Familiarity with industry-standard EDA tools and flows.
• Soft Skills: Self-motivated with a proactive approach to problem-solving.
• Strong communication and interpersonal skills.
• Ability to work independently and as part of a global team.
• More information about NXP in India... #LI-f91b