Principal Physical Design Engineer

What You'll Do

• /Expectations As the NVM IP Back‑End Design Lead for our newly formed Bangalore team, you will be part of a global NVM design organization.
• You will lead the back‑end design competence for a wide range of disruptive NVM IPs targeting Automotive MCUs, MPUs, and beyond.
• Your responsibilities will include: Lead and perform all functions in RTL2GDS flow including Synthesis, Floor-Planning, Power Distribution, Clock Tree Synthesis, Place and Route, ECO’s, and Chip Finishing with Metal/Dummy Fill Run Physical Verification Leverage AI tools to develop efficient and automated Physical design flows Team up with NXP NVM design team in Bangalore, EU and US Mentor junior engineers growing in the NVM field Specific skills & knowledge BS or MS in Electronics or Electrical Engineering with +10 years of experience in place and route design Hands-on experience on quality-managed Analog-Mixed signals design flows, tools and methodologies (Cadence and Synopsys) Hands-on experience in scripting and flow automation Must show expertise in either Cadence or Synopsys tools; but it is preferrable to be flexible between the two toolsets Experience in 1X/FinFET nodes and below for Place & Route Knowledge of NVM technology, macro architecture and design is highly desired, but not mandatory Excellent communication skills with proven experience in international relationships and available for occasional travel.
• More information about NXP in India... #LI-9415