Senior Principal Digital Design Engineer

What You'll Do

• Ownership of a sub system Digital circuit design and optimization (power, timing, area) including reusability IP evaluation and selection RTL coding Support functional simulations, give inputs for functional coverage SoC clock architecture Coverage analysis, lint and CDC analysis Support for backend in timing closure, develop timing constraints Support design for testability Support for power analysis Guide and mentor team members Review outputs from the design team HW-SW co-design and alignment with SW engineers Debug issues in netlist verification (0 delay, SDF simulations) Support for evaluation and verification of silicon Documentation (Datasheet, design reports) Support analysis of field problems Effort estimation and inputs for planning.
• Profile: 12+ years of experience in digital design, SoC integration.
• Expert in AMBA protocols Knowledge of ARM based SoC architecture Familiar with CPF/UPF formats Good knowledge of digital timing concepts, DFT concepts Experience in using functional simulation tools, synthesis tools, Spyglass Good communication skills in English Good team player eager to develop best in class products More information about NXP in India... #LI-7013