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Qualifications
- Some experience in RTL design of complex digital IP is desireable but not required Knowledge in Verilog RTL design, logic synthesis, coverage analysis and timing closure Understanding of IP development methodology and proficiency in front-end design tools Knowledge of state-of-the-art networking technologies including TCP/IP protocols is desirable but not required Experience with data products such as routers, bridges and switches is desirable.
- Security/cryptography experience would be an asset Strong architecture and design skills are desirable but not required Should be familiar with hardware and software implementation trade-offs.
- Ability to solve system wide problems.
- Algorithm development experience is desirable but not required Must work well in a team environment.
- Strong interpersonal, communication, and documentation skills.
- Bachelors in Computer Science, Engineering or related education required. 2+ years relevant experience Job location: Ottawa, Canada More information about NXP in Canada... #LI-e41b
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
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646 positions
Job ID
/job/Kanata/Logic-Design-Engineer_R-10063873-1
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