Lead Physical Design Engineer

What You'll Do

• Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). * Collaborate with physical verification (DRC, LVS, Antenna) and resolve related issues. * Collaborate with power integrity analysis (IR drop, EM) and optimize designs for power efficiency. * Collaborate with design, verification, and DFT teams to ensure seamless integration and achieve project milestones. * Analyze and resolve design issues related to timing, area, and power. * Develop and maintain scripts for automation and efficiency improvements in the physical design flow. * Contribute to the continuous improvement of physical design methodologies and flows. * Generate comprehensive reports and documentation of design implementation.
• Job Qualifications * Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field. * Minimum 8 years of experience in digital physical design of complex SoCs or ASICs. * Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime, Mentor Calibre). * Solid understanding and experience of physical design concepts including floorplanning, placement, routing, clock tree synthesis, and physical verification. * Strong knowledge of Static Timing Analysis (STA) and timing closure techniques. * Experience with scripting languages such as Tcl, Perl, or Python. * Familiarity with deep sub-micron process technologies. * Good understanding of VLSI design principles and semiconductor physics. * Excellent problem-solving skills and attention to detail. * Ability to work effectively in a collaborative team environment. * Good communication skills, both written and verbal.
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