ASIC Physical Design Engineer

About This Role

• Skills and responsibilities: Utilize commercial and in-house EDA tools (e.g.
• Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
• Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g.
• Placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis).
• Some knowledge of front end design and synthesis is advantageous Proficiency in UNIX/Linux and scripting languages, e.g. tcl, bash Required Qualifications: Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
• Minimum of 5 years or more experience in a relevant field.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.