Lead DFT Engineer

Overview

• Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS.
• He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis.
• Should have proficiency in industry-standard DFT tools such as Mentor Tessent , Synopsys DFT Compiler, Cadence Encounter Test.
• Should be able to contribute to ATPG at partition and SoC level.
• Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis.
• Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
• Effective communication and teamwork skills, with the ability to collaborate across functions.
• More information about NXP in India..