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What You'll Do
- Define and implement DFT architecture including scan, MBIST, and boundary scan.
- Perform scan insertion , chain stitching, and compression techniques.
- Generate and analyze ATPG patterns to achieve high fault coverage.
- Debug and resolve DFT-related issues across design and silicon stages.
- Work closely with RTL, Physical Design, and STA teams for smooth integration.
- Support pattern validation, gate-level simulations, and silicon bring-up .
- Ensure compliance with DFT and testability requirements .
- More information about NXP in India... #LI-2734
Sourced directly from NXP Semiconductors’s career page
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Specialisation
Salary range
₹5-10 LPA to ₹35-58 LPA
Open roles at NXP Semiconductors
716 positions
Job ID
/job/Noida/Sr-DFT-Engineer_R-10064454
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