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About This Role
- The Role and Impact: As a DFT Design Engineer, you will play a vital role in shaping the quality and performance of Intel's silicon products.
- You will contribute to the development of cutting-edge technologies by designing and verifying robust Design for Test (DFT) features that ensure manufacturability and reliability.
- Your work will directly impact Intel's ability to deliver high-quality products to market quickly, meeting both performance and quality objectives.
- This position offers the opportunity to collaborate with cross-functional teams, influence design methodologies, and drive innovation in test strategies for SoC and functional IP blocks.
- Key Responsibilities: Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP.
- Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems.
- Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals.
- Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation.
- Review and execute verification plans to ensure design features meet architecture specifications.
- Resolve RTL test failures and implement corrective measures to ensure feature correctness.
- Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs.
- Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE).
- Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements.
Requirements
- to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- This is an entry level position and will be compensated accordingly.
- Intel’s sponsorship guidelines: Learn more Link: Intel Careers Minimum Qualifications: Bachelor’s degree in computer or electrical engineering, or a related field with no prior experience required. 6+ months of experience with design tools 6+ months with RTL coding and DFT techniques.
Nice to Have
- Master's in computer engineering or computer science with 6+ months of experience Familiarity with test architecture including SCAN, MBIST, BSCAN, and TAP.
- Familiarity with RTL coding, DFT techniques, and timing closure methods.
- Experience with design tools and methodologies such as ATPG and coverage analysis.
- Experience configuring EDT setups and resolving stuck-at and at-speed test scenarios.
- Proficient programming skills in TCL, Python, Perl, and/or C++.
- Knowledge of GLS for test scenario resolution and ATPG coverage analysis Strong communication and collaboration skills, with a focus on teamwork across diverse engineering groups.
- Join us in advancing Intel's legacy as a technology leader.
- Apply today to be a part of our journey in innovating the future of silicon design and manufacturing.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Salary range
₹5-10 LPA to ₹35-58 LPA
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Job ID
/job/US-Colorado-Fort-Collins/DFT-Design-Engineer_JR0285455
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