Junior Layout Engineer

What You'll Do

• Delivering floorplan activities at IP level.
• Participating to the power supply strategy, signals distribution between blocks.
• Delivering Analog layout blocks.
• Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries.
• Participating to design reviews, write documentation and support for integration into products.
• Having a strong focus on design for quality (designs are properly verified, validated, and tested for long-term reliability and zero defect).
• Being able to leverage layout expertise to provide technical training and write technical guidelines Your Profile 0-2 years of experience leading Analog layout activities in complex ICs MSEE/BSEE or working equivalent Experience in Analog layouts, device physics, and IC ESD protection strategies Experienced in layout design tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics (Calibre) Ability to drive and collaborate with experienced people having different technical profiles Experience in delivering advanced floorplan strategies Experience in physical implementation in Analog blocks at IP level Experience with cross functional teams and excellent communication skills to operate in a global environment with multiple partners in design, test, program management, quality department More information about NXP in Italy... #LI-7795