DSP Architect

Overview

• Role Summary: As a DSP Architect, you will be responsible for the design, implementation, and verification of digital signal processing functions at the IP, subsystem, or IC level.
• You will work on advanced digital and mixed-signal systems, focusing on high-speed, low-power design, and robust control loop implementation.
• Your work will directly contribute to the development of next-generation networking and automotive solutions.
• DSP Architecture & Algorithm Development Architect and model DSP algorithms for Automotive Ethernet PHYs including Echo cancellation Timing recovery, equalization (FFE/DFE), scrambler/descrambler PAM3/PAM4 modulation schemes LDPC/FEC coding and decoding Define end‑to‑end DSP signal chains with clear performance, latency, and power budgets.
• Own MATLAB/C‑modeling, simulation, performance analysis, and fixed‑point conversion strategies.
• Optimize DSP blocks for power, area, and performance trade‑offs in automotive SoCs.
• Standards & Compliance Ensure full compliance with IEEE 802.3 Automotive Ethernet specs and emerging standards.
• Drive interoperability and compliance testing strategies (OPEN Alliance, UNH‑IOL, OEM‑specific requirements).
• Evaluate TSN‑related DSP requirements and contribute to system‑level determinism features.
• System & Architecture Leadership Define PHY architecture interacting with analog/RF, mixed-signal, and digital teams.
• Perform system‑level modeling, channel modeling, and link‑level simulations.
• Work closely with IC architects to partition functionality between DSP hardware, firmware, and analog blocks.
• Generate design documents, architecture specifications, and algorithm performance reports.
• Cross‑Functional Collaboration Partner with IC design, verification, firmware, and validation teams for design bring‑up and silicon debug.
• Support customer engagements, requirements definition, and technical reviews with OEMs and Tier‑1s.
• Provide guidance to implementation teams on micro‑architecture, resource requirements, and performance constraints.