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About This Role
- An STA (Static Timing Analysis) Design Intern is responsible for evaluating the timing margins of semiconductor logic designs (ASIC/SoC) to ensure the chip will function at target speeds without errors.
- Key tasks include running timing constraints, analyzing slack, and fixing setup/hold violations.
- Key Responsibilities: Perform Static Timing Analysis (STA) : relating tasks such as kicking off runs, perform timing analysis and timing fixes.
- Constraint management : Assist senior engineers in creating, updating and debugging timing exceptions.
- Scripting: Write scripts to enhance/speed up the process of the current available flows.
Qualifications
- Third-year or Final-year student currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or VLSI Systems or a closely related field (Physics, Maths).
- Be able to work onsite for 4 days per week.
- Be able to commit to at least a 6-month internship program.
- Strong verbal and written communication skills in English.
- Knowledge Base: Strong foundational grasp of digital logic, flip-flops, clock domains, and CMOS circuit design.
- Tools: Familiarity with Linux environments and basic exposure to EDA tools.
- Programming: Proficient in scripting languages (Tcl, Python, or Perl) and hardware description languages (Verilog or SystemVerilog).
- Soft Skills: Strong analytical and problem-solving skills, paired with a collaborative team spirit and a passion for continuous learning.
- Benefit Package of Interns at Intel Vietnam Attractive internship allowance Training programs, opportunities to be involved in multinational projects.
- Exciting extracurricular and sports programs for employees Well-invested facilities, putting safety first.
- Shuttle bus system at many places in Ho Chi Minh City, Binh Duong, Dong Nai.
- High-quality cafeteria, lunch allowance.
- Safe, stable and dynamic working environment.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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598 positions
Job ID
/job/Vietnam-Ho_Chi_Minh_City/STA--Static-Timing-Analysis--Design-Intern_JR0285659
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