Soc Subsystem Architect - AI platform Development

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About the Role Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators.
If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role.
Join us to shape the future of AI hardware Responsibilities • Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations. • Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs. • Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects. • Develop and maintain timing constraints for IP blocks; provide guidance and support to physical design teams for synthesis, timing closure, and formal equivalence checks. • Drive silicon bring-up and post-silicon validation, including debug and performance analysis. • Mentor junior engineers and contribute to best practices for design methodology and quality.

are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Basic Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. • 10+ years of experience in RTL design and implementation for ASIC/SoC development.
Preferred Skills and Experience • Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure. • Hands-on experience with SoC system integration and multicore CPU subsystem design. • Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures. • Expertise in high-speed and low-power design techniques. • Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization. • Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II). • Ability to thrive in a dynamic environment with evolving requirements. • Strong communication skills, collaborative mindset, and leadership qualities. • Passion for innovation, continuous learning, and tackling technical challenges.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

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