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About This Role
- Candidate will be part of SoC Clocking team and will work on next generation of Server SoC designs.
- In this role, candidate will be part of product pathfinding, clock distribution and driving overall SoC clock implementation and Sign off.
- Responsibilities include but are not limited to the following: - Must have Experience in SoC Clock Architecture, clock distribution and system level clocking. - Experience in clocking IPs PLL, DLL etc. - Hands on experience with spice, clock jitter simulations and different jitter components. - Clocking methodologies and guidelines for IPs or SoCs. - Creates scalable flows for clocking infrastructure for better performance and power in the design. - Working with Platform, package, IP and SoC design team for driving best in class clocking solutions. - A good knowledge of Physical design and SoC timing analysis would be helpful. - Perl, TCL Scripting Skills.
Qualifications
- Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering or related areas. - At least 10+ years of experience in SoC clock architecture, clock distribution and clock implementation. - Hands - on experience with Synopsys, cadence APR/Clock implementation tools - Good understanding of System level clocking. - Proficient in scripting languages (Tcl, Perl, Python). - Ability to communicate effectively with multiple global cross-functional teams.
Sourced directly from Intel’s career page
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Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
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98 positions
Job ID
/job/India-Bangalore/SoC-Physical-Design-Clocking-Engineer_JR0284438
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