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About This Role
- Intel Central Engineering Group is seeking Physical Design Engineers to join our dynamic team and contribute to the development of cutting-edge custom IP and SoC designs for Intel products and Intel Custom ASIC Customers.
- In this role, you will play a pivotal part in translating RTL to GDS, enabling manufacturing-ready design databases that drive innovation in products.
- Performs and lead physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
- Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
- Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
- Analyzes results and makes recommendations to fix violations for current and future product architecture.
- Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
- Optimizes design to improve product level parameters such as power, frequency, and area.
- Participates in the development and improvement of physical design methodologies and flow automation.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ Years of experience in Physical Design execution. - Master's degree with 6+ Years of experience in Physical Design execution. - Deep knowledge in RTL-to-GDS workflows, including synthesis, place and route, and static timing analysis. - Expertise in optimization techniques for power, performance, and area (PPA). - Hands-on experience with industry-standard EDA tools for physical design and verification. - Comprehensive knowledge of clock tree synthesis and low-power design techniques. - Experience with competitive timing, floor planning methodologies (TFM), and multi-power domain analysis.
Nice to Have
- Demonstrated ability to collaborate within cross-functional teams to achieve strategic design goals. - Strong critical thinking and problem-solving skills to manage complex design challenges. - Excellent communication and organizational abilities to coordinate across disciplines. - A passion for innovation and continuous improvement in design methodologies.
Sourced directly from Intel’s career page
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Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Intel
98 positions
Job ID
/job/India-Bangalore/Senior-Physical-Design-Engineer_JR0284422
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