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About This Role
- Join Intel as SOC Physical Design Engineer, where you will play a pivotal role in shaping the future of custom IP and SoC designs.
- In this position, you will drive the physical design implementation of cutting-edge technologies, transforming RTL to GDS databases ready for manufacturing.
- Your expertise in physical design flows will directly contribute to optimizing power, frequency, and area metrics, enabling Intel to deliver high-performance products that empower innovation worldwide.
- This is an opportunity to be part of a dynamic team where your work will have a meaningful impact on Intel's mission to push the boundaries of technology and deliver industry-leading solutions.
- Responsibilities Work on SOC floorplan, Pin and macro placement optimizing area and efficiency.
- Perform physical design implementation for custom IP and SoC designs across the entire design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
- Conduct verification and signoff activities such as formal equivalence verification, reliability verification, power integrity analysis, and layout verification using industry-standard EDA tools.
- Drive design optimization across multiple power domains, static and dynamic power integrity analysis, and structural design checking.
- Participate in the development and enhancement of physical design methodologies and flow automation.
- Collaborate with cross-functional teams to ensure designs meet product-level parameters, quality benchmarks, and are ready for manufacturing.
Requirements
- to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Requirements
- Bachelor's degree with 8+ years or master’s degree with 6+ years or PhD. with 4+ years in Electrical/ Electronic Engineering, Computer Engineering, Computer Science or a related technical discipline. 4+ years of experience with the following technical skills: Proficiency in physical design flows, including synthesis, place and route, clock tree synthesis, and static timing analysis.
- Expertise in design optimization for physical design, multi-power plane design (MPP/UPF), and RTL to GDS workflows.
- Hands-on experience with scripting to automate design flows.
- Knowledge of EDA tools and methodologies for verification, reliability, timing closure, and power integrity analysis.
Nice to Have
- Expertise in Design planning, Hierarchical design, SOC floorplan and optimizations.
- Strong analytical skills with the ability to identify and resolve complex design challenges efficiently.
- Effective communication skills and the ability to work collaboratively within a team-oriented environment.
- Experience developing and improving physical design methodologies and automation tools.
- Familiarity with industry trends and emerging technologies in physical design, ensuring designs remain forward-thinking and innovative.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Salary range
₹5-11 LPA to ₹38-65 LPA
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101 positions
Job ID
/job/US-Massachusetts-Beaver-Brook/Senior-Full-Chip-Physical-Design-Integration-Lead_JR0283815
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