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About This Role
- As a Physical Design Engineer, you will play a pivotal role in Intel's journey to delivering world-class custom IP and SoC designs.
- Embedded in a vibrant and collaborative environment, you will transform RTL into manufacturing-ready design databases, harnessing cutting-edge industry EDA tools and methodologies.
- Your contributions will directly influence Intel's ability to innovate at leading-edge process nodes, optimizing the design to achieve exceptional power, performance, and area (PPA) metrics.
- This is a unique opportunity to drive the development of next-generation technologies, leaving a lasting impact on Intel's product portfolio and its position as a global leader in semiconductor design.
- Key Responsibilities: Execute all stages of the physical design flow, including synthesis, floor planning, placement, routing, clock tree synthesis, and static timing analysis.
- Conduct verification and signoff activities such as formal equivalence verification, layout verification, reliability checks, and power/noise analysis.
- Drive timing closure efforts using industry-standard tools like Primetime, working to meet stringent design and signoff requirements.
- Analyze timing reports, debug issues, execute timing ECOs, and deliver feedback to optimize design methodologies.
- Develop and refine power/clock distribution strategies to ensure robust and efficient designs.
- Collaborate closely with architecture, design, and implementation teams to define constraints, clocking specifications, I/O budgets, and achieve IP budget convergence.
- Enhance design flows and automation processes to accommodate evolving technology and product architecture needs.
- Mentor junior engineers, fostering skill development and technical excellence within the team.
Requirements
- Bachelor's degree in Electrical or Computer Engineering, or related field, with 2+ years of experience; or a Master's degree with 1+ years of experience; or a PhD with 0 years of experience in the structural/physical design domain.
- Experience with the entire RTL-to-GDS flow, including physical design methodologies, STA, and timing signoff.
- Demonstrated expertise in EDA tools such as Primetime, ICC, or Innovus for physical design and verification tasks.
- Proficiency in scripting languages like Perl, TCL, and automation of design workflows.
- Solid understanding of low-power and advanced design techniques for deep sub-micron process nodes.
Nice to Have
- Multiple tape-out experiences on advanced technology nodes.
- Expertise in developing SDC constraints, timing budgeting, and ECO implementation.
- Familiarity with hardware description languages such as Verilog or VHDL.
- Proven ability to work collaboratively across diverse teams, with strong analytical and problem-solving skills.
- Join us in shaping the future of semiconductor design.
- Apply today and become an integral part of Intel's mission to push the boundaries of technology and innovation.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Salary range
₹5-11 LPA to ₹38-65 LPA
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101 positions
Job ID
/job/Malaysia-Penang/Physical-Design-Engineer_JR0284212
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