Physical Design Engineer

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About This Role

  • As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs, delivering cutting-edge solutions for high-performance computing applications.
  • Your contributions will span the complete physical design flow, from RTL to GDS, ensuring the highest levels of quality, performance, and manufacturability.
  • By leveraging your expertise in physical design methodologies and tools, you will have a tangible impact on Intel's industry-leading product portfolio, driving advancements in power efficiency, speed, and innovation.
  • This is a unique opportunity to join a collaborative team of engineers, tackle complex challenges, and contribute to the development of transformative technologies.
  • Key Responsibilities Execute RTL-to-GDS implementation of custom IP and SoC designs, including synthesis, place-and-route, clock tree synthesis, and floor planning.
  • Conduct comprehensive static timing analysis, power and noise analysis, and reliability assessments to meet stringent design specifications.
  • Perform verification and signoff, including formal equivalence verification, layout verification, and static and dynamic power integrity checks.
  • Identify and resolve design violations, optimizing for parameters such as power, frequency, and area.
  • Develop and refine physical design methodologies, leveraging EDA tools to enhance automation and workflow efficiency.
  • Collaborate with cross-functional teams, including architecture and logic designers, to define design requirements and ensure seamless integration.
  • Utilize scripting skills to automate repetitive tasks, enhance productivity, and debug design anomalies.
  • Drive continuous improvement in physical design processes to meet the demands of advanced process nodes and next-generation architectures.

Requirements

  • Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field. 6 or more years of experience in the structural/physical design domain with a Bachelor's degree, four or more years with a Master's degree, or two or more years with a PhD.
  • Proficiency in RTL-to-GDS tools and methodologies, including synthesis, place-and-route, clock tree synthesis, and floor planning.
  • Deep expertise in static timing analysis, including SDC development, timing budgeting, and timing signoff using tools such as Primetime.
  • Strong scripting skills in languages such as Perl, TCL, Python, or Shell, with the ability to automate workflows and debug issues effectively.
  • Extensive knowledge of EDA tools and flows, including low-power design techniques and multi-power domain analysis.
  • Experience in multiple tape-outs for deep sub-micron process nodes.
  • Preferred Qualifications Advanced experience in I/O and IP timing budget development.
  • Familiarity with Verilog or VHDL for hardware description and verification.
  • Proven track record of mentoring and developing junior team members.
  • Exceptional problem-solving skills, collaborative mindset, and ability to thrive in a diverse team environment.
  • Strong organizational and multitasking abilities, with a focus on delivering high-quality solutions under tight deadlines.
  • We encourage you to bring your expertise, creativity, and passion for innovation to Intel.
  • Join us in driving technological breakthroughs that shape the future.
  • Apply today and help us redefine what is possible.

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Intel

Malaysia, Penang

Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Intel
101 positions
Job ID
/job/Malaysia-Penang/Physical-Design-Engineer_JR0284208

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