Senior Design Verification Engineer

About This Role

• The Role and Impact: Intel is seeking a Design Verification Engineer for the Silicon Chassis team.
• In this role, you will independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance.
• You will build and drive robust verification plans, develop scalable reusable environments, and take direct accountability for quality and schedule on your assigned blocks.
• You will work closely with architecture, design, and software teams and are expected to contribute across traditional discipline boundaries.
• This role requires strong DV depth, solid protocol knowledge, hands-on coding strength, and growing ability to mentor junior engineers.
• AI-assisted workflows are part of everyday development here.
• Consistent execution against schedule and quality goals is expected.
• Key Responsibilities: - Own verification planning and execution for assigned IP blocks and features at IP and subsystem level; drive test plans through coverage closure with direct accountability for quality. - Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure; take ownership of the verification collateral you deliver. - Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed to unblock progress, - Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication, own debug for your blocks end-to-end. - Drive functional coverage planning and coverage closure for assigned blocks; contribute to quality signoff with increasing independence. - Continuously improve verification automation, regression quality, and development efficiency. - Begin mentoring junior engineers on verification practices, debugging techniques, and code quality.