Analog IP Design Execution Manager

About This Role

• The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industrydefining analog and mixedsignal IP for Intel's Client, Datacenter, AI and Foundry customers.
• The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes.
• As an IP execution leader, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.
• This IP execution leader role will be responsible for the following: • All aspects of the integrated IP planning, execution, and delivery from initial engagement with SOC partners, conceptual planning and tech readiness, pre-silicon execution, post-silicon validation and launch.
• This leader coordinates across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliver IP releases on time and with committed content and quality. • Knowing enough detail about the execution of the IP program that you can adeptly speak to program status and risks using data, metrics, and trends. • Drawing on prior design experience, identify technical problems and take the lead to drive solutions. • Ensuring appropriate progress against schedule, recommend recovery actions and mitigate issues. • Drive efficient, effective, and transparent decisions to keep IP execution tracking positively toward aggressive and achievable deliverables. • Clear, appropriately leveled communication to a range of audiences spanning engineers, technical leaders, and executives. • Establishing productive, collaborative relationships with peers, partners, and stakeholders spanning SOC, IP design, and post-silicon validation teams. • Maintaining strong connections with other IP execution leads and partners located in both the US and globally. • Conduct retrospective reviews to drive continuous improvements in execution efficiency and product quality. • Driving results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.
• This is an on-site role and you are expected to work in the office at least 4 days per week.
• You are a competitive candidate for this job if you possess these skills and competencies: • Strong results orientation and great aptitude for problem-solving. • Ability to see a challenge on the horizon and plan for it. • You are skilled and comfortable facilitating direct and open communication. • You work naturally and readily with a wide range of contributors: technical leads, manager peers, partner teams, senior technologists, executives, and other organizations. • You can articulate ideas and key messages succinctly. • Demonstrated success leading large-scale, cross-functional programs with aggressive timelines and complex external dependencies. • Ownership mindset with a high degree of urgency and accountability for execution results and customer success. • Solid understanding of the end-to-end silicon lifecycle, from architectural definition through production qualification and release. • Familiarity with AI/ML-driven design productivity techniques, automation frameworks. • Proven experience executing complex mixed-signal and/or high-speed serial IP development in advanced semiconductor process nodes.