RTL Design Engineer

About This Role

• We are seeking a Senior RTL Design Engineer with 5+ years of experience to drive the logic design and integration of our next-generation, high-speed Mixed-Signal IP.
• In this role, you will bridge the gap between digital architecture and analog mixed-signal (AMS) circuits, taking ownership of critical digital blocks that control, calibrate, and interface with high-speed SerDes components.
• You will collaborate closely with analog designers, verification engineers, and architectural teams to deliver robust, power-efficient, and highly optimized silicon IPs compliant with the latest specifications.
• Key Responsibilities RTL Development: Own the micro-architecture and RTL design (using SystemVerilog/Verilog) for digital control blocks within the PHY, including PCS (Physical Coding Sublayer), calibration engines, power management states (L0s, L1, L2), and clock/reset distribution.
• Mixed-Signal Interface and Integration: Define, design, and verify the digital-analog interface boundary.
• Implement complex calibration algorithms for analog components (e.g., RX equalization, TX driver impedance, PLL/DLL tracking loops).
• IP Compliance: Ensure the digital logic seamlessly integrates with the Data Link layer via standard interfaces (such as PIPE 5.x/6.x) and strictly adheres to protocol constraints.
• Front-End Implementation: Drive design closure activities including Linting, Clock Domain Crossing (CDC) analysis, Formal Verification (LEC), and Static Timing Analysis (STA) constraints generation.
• Collaboration and Debug: Work hand-in-hand with Analog Mixed-Signal (AMS) simulation teams and Design Verification (DV) teams to debug complex co-simulation failures and maximize functional coverage.
• Silicon Power-On Support: Support post-silicon validation, bring-up, and debug teams to root-cause silicon misbehavior and optimize firmware/hardware calibration parameters.