Research Intern for Supernode Solution

About This Role

• Intel DCG China is seeking a passionate, self-motivated, and talented Research Intern to work on Scale-up Protocols and Memory Pooling for KV Cache-Centric Systems Qualifications: Responsibilities System Innovation and Cost Optimization for Disaggregated Supernode Architecture o Explore architectural innovations for disaggregated AI supernode designs, with a focus on system-level performance trade-offs, BOM cost reduction strategies, and scalability from NPI to HVM.
• GPU Interconnect Protocol and Memory Pooling Implementation o Research and prototype Ethernet-native GPU interconnect protocols and distributed memory pooling mechanisms for large-scale AI inference and training clusters.
• Qualifications Master's student in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Familiarity with core RDMA operations, including one-sided read/write, Send/Receive verbs, QP management, and memory registration.
• Hands-on experience with Mellanox ConnectX-7 testing and diagnostic tools, including perftest, ibstat, mlnx_tuning, and OFED utilities.
• Working knowledge of LLM inference benchmarking methodology and standard metrics (TTFT, TBT, token/s), with experience using frameworks such as vLLM, lm-evaluation-harness, or equivalent.