Principal Design Engineer – AI SoC / Subsystem Lead

3 Locations SoCHigh demand

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About This Role

Intel’s AI SoC organization develops cutting-edge products powering a wide range of AI applications—from edge devices to data center accelerators.
If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, this is your chance to shape the future of AI hardware.
Role Overview As a Senior SoC Design Engineer, you will be responsible for defining, implementing, and validating complex SoC IP blocks and subsystems, ensuring they meet stringent power, performance, and security requirements.
You will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon for next-generation AI solutions.
Key Responsibilities Architectural Leadership: Evaluate trade-offs across features, performance targets, power constraints, and system limitations.
Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver synthesis- and timing-clean designs.
Verification Collaboration: Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
Timing & Physical Design Support: Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.
Silicon Bring-Up: Drive post-silicon validation, debug, and performance analysis.
Mentorship & Methodology: Mentor junior engineers and contribute to best practices for design methodology and quality.
Additional Responsibilities Perform quality checks across RTL, timing, and power convergence.
Apply secure development practices to address security threat models and objectives.
Collaborate with IP providers for integration and validation at the SoC level.
Drive compliance for smooth IP-to-SoC handoff.
Additional Skills: Ability to lead projects, work cross-functionally, and deliver under tight schedules Strong communication skills and a collaborative mindset Qualifications: Minimum Qualifications • Bachelor's or master's degree in electrical engineering, Computer Engineering, or Computer Science or related field with 10+ years of experience. • 7+ years of experience in RTL design and implementation for ASIC/SoC development.
Preferred Qualifications • Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure. • Hands-on experience with SoC system integration and multicore CPU subsystem design. • Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures. • Expertise in high-speed and low-power design techniques. • Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization. • Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).

Benefits

We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Find out more about the benefits of working at Intel .
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

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