Physical Design for PPA Optimization Engineer

About This Role

• Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs.
• Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology.
• We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products.
• Role Overview As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs.
• You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction.
• Key Responsibilities Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation.
• Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure Run the full PnR flow to evaluate new technology impacts on PPA metrics.