Lead Physical Design Engineer

What You'll Do

• Lead and perform RTL Synthesis & comprehensive Static Timing Analysis (STA) at the block, sub-system, and SoC levels for cutting-edge semiconductor designs. * Develop, integrate, and maintain timing constraints (SDC) for various design hierarchies, ensuring accuracy and coverage. * Identify, debug, and resolve complex timing violations, including setup, hold, and other advanced timing checks (e.g., OCV, AOCV, EMIR, X-talk). * Collaborate closely with design, DFT, physical design, and verification teams to ensure timing closure and meet project deadlines. * Develop and implement efficient STA methodologies, flows, and scripts to improve productivity and turnaround time. * Perform timing sign-off activities and generate comprehensive timing reports for internal and external reviews. * Mentor and provide technical guidance to junior engineers, fostering a culture of continuous learning and improvement. * Stay updated with industry trends, best practices, and new technologies in STA and physical design.
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