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About This Role
- Join our dynamic team as a Physical Design Engineer, where you'll play a pivotal role in delivering cutting-edge custom IP and SoC designs that drive Intel's innovative products.
- You'll be a key contributor to the physical design flow, ensuring that designs transition seamlessly from RTL to GDS and are optimized for manufacturing.
- By leveraging your technical expertise, you will directly impact the power, performance, and area of our designs, enabling Intel to maintain its leadership in the semiconductor industry.
- This position offers an exciting opportunity to work on advanced technology nodes and collaborate with cross-functional teams to develop next-generation solutions.
- Key Responsibilities Perform physical design implementation of custom IP and SoC designs, from RTL to GDSII finalization.
- Execute tasks in the physical design flow, including floorplanning, synthesis, place and route, clock tree synthesis, and static timing analysis.
- Conduct verification and signoff for formal equivalence, timing, reliability, power integrity, and layout.
- Identify, analyze, and resolve violations in timing, power, and noise to ensure optimal design quality.
- Collaborate on chip partitioning, pin placement, power distribution, and congestion mitigation to optimize physical layouts.
- Utilize and enhance design methodologies and automation flows to improve efficiency and accuracy.
- Leverage industry-standard EDA tools for tasks such as synthesis, routing, and timing closure (e.g., Fusion Compiler, IC Compiler II, PrimeTime).
- Perform ECO (Engineering Change Order) implementation and top-level physical verification signoff.
- Partner with cross-site and cross-functional teams to innovate and deliver results aligned with Intel's strategic goals.
Requirements
- Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of experience, or a Master's degree and 2+ years of experience, or a PhD with no required experience.
- Proficiency in RTL to GDSII tools, including Fusion Compiler, Design Compiler, IC Compiler II, and PrimeTime.
- Strong expertise in physical design workflows, including floor planning, synthesis, place and route, clock tree synthesis, and static timing analysis.
- Hands-on experience with scripting languages such as Python, Perl, and TCL for flow automation.
- In-depth knowledge of hardware description languages such as Verilog or VHDL.
- Familiarity with Unix-based systems and shell scripting.
- Preferred Qualifications Proven track record of multiple tapeouts in deep submicron technology nodes.
- Experience in DDR design or other high-speed interfaces.
- Background in block-level and full-chip floor planning, power grid design, and power optimization techniques.
- Demonstrated ability to lead key technical initiatives and deliver complex physical databases for ASICs, SoCs, or IPs.
- Strong problem-solving skills with expertise in debugging simulation and verification failures.
- Excellent written and verbal communication skills to collaborate effectively with global teams and stakeholders.
- Apply today to be at the forefront of shaping the future of semiconductor technologies with Intel's world-class team.
Sourced directly from Intel’s career page
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₹5-11 LPA to ₹38-65 LPA
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/job/Malaysia-Penang/Physical-Design-Engineer_JR0284215
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