Physical Design Engineer

About This Role

• The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure.
• The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with Physical Design, STA, and Methodology teams while operating within established SAM signoff frameworks.
• We invite you to apply and be part of our mission to deliver world-class semiconductor solutions.
• Join us in shaping the future of technology.
• Responsibilities will include but are not limited to: Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
• Conduct verification and signoff, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and timing analysis.
• Identify and resolve violations, making recommendations for current and future product architectures.
• Optimize designs to enhance metrics such as power, frequency, and area using industry-standard EDA tools.
• Develop and improve physical design methodologies, automation flows, and processes.
• Possess expertise in structural and physical design, including timing closure, physical clock design, and multiple power domain analysis.
• Define and apply constraints for hierarchical design integration and floor planning concepts.
• Collaborate with cross-functional teams to ensure designs meet Intel's quality and performance standards.
• The ideal candidate should show the following behavioral traits: Strong cross-team collaboration skills.