Mixed Signal Logic Verification Engineer

About This Role

• A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/SystemVerilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug.
• Key responsibilities include defining verification plans, guiding junior engineers, improving verification methodologies, ensuring coverage closure, and collaborating with architects for top-level verification.
• Key Responsibilities: Strategy & Planning: Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs.
• Methodology: Design and maintain advanced test benches, scoreboards, and checkers using SystemVerilog and UVM.
• Technical Leadership: Mentor junior engineers, conduct code reviews, and drive verification closure to meet project milestones.
• Debug & Analysis: Perform RTL debug, gate-level simulations, and functional/code coverage analysis.
• Collaboration: Work with architects and design teams to identify, debug, and resolve issues, including post-silicon failures.
• Formal Verification: Utilize formal methods (e.g., model checking) to verify complex, hard-to-reach corner cases.