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What You'll Do
- Define and implement SoC level DFT architecture for large and complex designs.
- Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
- Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
- Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
- Support post-silicon debug, failure analysis and yield learning.
- Collaborate with RTL, verification, physical design and operation teams.
Qualifications
- BS degree At least 3 years of hands-on experience in SoC DFT.
- Must-have skills: Strong expertise in SCAN, ATPG, MBIST.
- Experience with pre-silicon validation and post-silicon debug.
- Strong problem solving and debugging skills.
- Ability to work effectively in a cross-functional engineering environment.
- Good-to-have skills: Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
- Experience with IP-level DFT integration and reuse.
- Exposure to low-power DFT considerations and complex clocking architectures.
- Familiarity with manufacturing test flows and silicon yield improvement.
- The annual salary range for California is $88,900 to $165,100.
- You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
- Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
- Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
- Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
658 positions
Job ID
/job/CARY/Design-Engineer-I_R56021
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