Custom Layout Designer (Analog Layout Designer)

What You'll Do

• all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules.
• The Cadence IP Group custom layout team develops and delivers a variety of high-quality high speed and high accuracy CMOS integrated circuits IP for several foundries and process nodes down to 5n and even below.
• We are deeply involved in finfet layout and even beyond (gate all-around).
• As part of Cadence, the Cadence IP group custom layout team not only has access to all the current and future Cadence layout and verification tools, we also participate in the development and validation of the Cadence Virtuoso software, which the most used in the industry.
• As a custom layout designer, you will be involved in: Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency Working with custom layout designers from groups all over the world to build high quality IP and test-chips Working with circuit designers from groups all over the world to understand their technical and schedule needs Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools BSEE, MSEE Exposure to microelectronics design and requirements Understanding of layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques like matching, shielding etc., Exposure to Cadence Virtuoso Layout and physical verification tools Team player, driven, self-motivated and autonomous Excellent communication, presentation and customer service skills We’re doing work that matters.
• Help us solve what others can’t.