Staff Analog Design Engineer

What You'll Do

• LeadtechnicalfeasibilityofinnovativearchitecturesforIPmacro-blockswithinPowerICs,i.e.power-stages, gate drivers and various sub-systems (control, diagnostics, monitoring, telemetry, voltage/current/timing references, internal supplies, etc).
• Explore, compare and derive KPIs and achievable specs for various architectural and process technology options by means of mathematical/prediction models, circuit models, existing designs and/or lab evaluation data.
• Hands-on custom design of analogue/mixed-signal IP macro-blocks in planar and FinFET technologies.
• Lead and own design, pre- and post-layout verification (block- and top-level), spec compliance matrix, behavioural modelling, layout implementation, and documentation.
• Provide guidance, reviews and CAPA to IP-level floorplan and layout implementation of analogue/mixed-signal blocks, with attention to matching, shielding, routing, parasitic, electromigration, DFM, area optimization, etc.
• Run layout parasitic extraction and post-layout back-annotated simulations.
• Interface to the IC Design Lead and development teams to enable smooth IPintegration into IC top-level Interface with engineering teams outside analogue design (i.e., passive design, package design, digital design, verification) for what matters to the IP macro-blocks being responsible for.
• Support the lab evaluation team and/or take ownership of silicon lab validation of the designed IP macroblocks as required.
• Support test engineering and operation teams for product characterisation and qualification.
• Coordinate tasks of junior colleagues or external sub-cons: distribute, monitor, review, and improve quality of Qualifications: MS in Electrical Engineering with 5+ years' experience in power IC design or 8-12 years in analogue/mixed-signal IC design.
• Expert-level proficiency with Cadence Virtuoso and simulation Strong understanding of analogue/mixed-signal design and layout techniques: CMOS process technology manufacturing, offset, noise, efficiency, current density, ESD, reliability, test & trim, thermals.
• Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment, including cross-site collaboration (i.e.
• US and other locations).
• Experiencewithhands-onparasiticanalysis,post-layoutcircuitsimulationandparasiticoptimizationis Excellent communication skills (verbal, written) with the ability to present complex technical topics using simple and effective communication when needed, as well as the ability to deep-dive into technical details if required.
• Experience in lab silicon validation of IPs within PMIC / Power ICs is desirable #LI-EC1 For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days