Sr. Principal Digital Design Engineer

What You'll Do

• IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.
• Requirements: BSEE or equivalent required, MSEE is a plus, with 12+ years of related experience in following areas preferred: - Strong Verilog/SystemVerilog coding skills. - Working knowledge of ASIC front-end design flows. - Working knowledge of C/C++. - Working experience of design verification techniques and test bench development.
• Strongly desired: Working knowledge of UVM is a desirable Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus Working experience of Unified Power Format for simulation, synthesis and CLP checking is a plus Good knowledge of scripting languages.
• Perl and Python are plusses.
• More information about NXP in India... #LI-2734