SoC Front End Design Engr

What You'll Do

• Participate in the architectural definition and micro-architecture development of SoC blocks and sub-systems. * Perform RTL design and coding (Verilog/SystemVerilog) for various digital blocks, ensuring adherence to design specifications and best practices. * Conduct extensive design verification activities, including testbench development, simulation, and debugging, to achieve functional correctness. * Collaborate with verification engineers to define test plans, coverage goals, and resolve design issues. * Execute and analyze various front-end design flows, including linting, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and formal verification. * Perform synthesis and timing analysis (STA) to meet performance targets and ensure timing closure. * Work closely with backend teams during physical design implementation and post-layout verification. * Contribute to documentation of design specifications, micro-architecture, and verification plans. * Participate in design reviews and provide technical feedback. * Identify and implement opportunities for design optimization in terms of area, power, and performance. --- Qualifications * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field. * 4-7 years of experience in SoC Front End Design. * Strong proficiency in RTL design using Verilog/SystemVerilog. * Solid understanding of digital design fundamentals, computer architecture, and SoC design methodologies. * Hands-on experience with industry-standard EDA tools for simulation, synthesis, linting, CDC, and STA. * Familiarity with scripting languages such as Perl, Python, or Tcl. * Knowledge of UVM/OVM methodologies is a plus. * Experience with low-power design techniques is desirable. * Excellent problem-solving, analytical, and debugging skills. * Strong communication and interpersonal skills, with the ability to work effectively in a team environment. * Ability to work independently and manage multiple tasks in a fast-paced environment.
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