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What You'll Do
- Own full‑chip static timing analysis and signoff for advanced‑node SoC designs.
- Develop and maintain STA constraints (SDC) and timing methodologies.
- Perform block‑level and top‑level timing analysis, debug violations, and guide design teams toward closure.
- Work with RTL, synthesis, and physical design teams to resolve setup/hold, clock skew, noise, and transition issues.
- Optimize timing through constraint refinement, logic restructuring suggestions, ECO guidance, and physical optimization feedback.
- Analyze and validate timing models, including Liberty (.lib), SPEF, and SDF.
- Support timing‑related signoff flows, including OCV/AOCV/POCV, crosstalk analysis, and MCMM timing closure.
- Provide technical leadership in methodology development, tool evaluation, and flow automation.
- Collaborate with cross‑functional teams (DFT, power, architecture) to ensure consistent timing across all design modes and corners.
- Mentor junior engineers on STA fundamentals, flow usage, and debugging techniques.
Qualifications
- Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Strong English communication skills , including the ability to collaborate effectively with global teams and clearly articulate technical issues in English. 5+ years of hands‑on STA experience in SoC development.
- Strong proficiency with industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
- Solid understanding of timing concepts such as OCV/AOCV/POCV, clock tree synthesis, crosstalk, IP timing integration, and MCMM flows.
- Familiarity with synthesis, place-and-route, and ECO flows.
- Expertise with SDC constraints and timing debugging.
- Strong scripting skills in Tcl, Perl, Python, or Shell.
- Excellent problem‑solving abilities and communication skills.
- More information about NXP in Greater China... #LI-6650
Sourced directly from NXP Semiconductors’s career page
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Specialisation
Open roles at NXP Semiconductors
541 positions
Job ID
/job/Tianjin-Teda/Senior-Static-Timing-Analysis--STA--Engineer_R-10062645
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