Senior Digital Verification Engineer

Qualifications

• BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.
• Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.
• Expertise in Verilog, SystemVerilog, UVM/OVM, and class-based verification methodologies.
• Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.
• Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP.
• Experience with SystemVerilog Assertions (SVA), formal verification techniques, and low-power verification methodologies such as UPF/CPF.
• Knowledge of industry-standard protocols including AMBA, I²C, SPI, UART, CAN, LIN, DDR, and PCIe.
• Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation.
• Familiarity with FPGA, emulation, or prototyping platforms such as HAPS, Palladium, or Zebu is a plus.
• Understanding of PMIC architectures and power management concepts is highly desirable.
• Experience using AI/LLM-based technologies to improve engineering productivity is a plus.
• Strong analytical, debugging, problem-solving, communication, leadership, mentoring, and cross-functional collaboration skills.
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