Associate Design Verification Engineer

What You'll Do

• Develop and execute test benches for digital and mixed-signal design verification using SystemVerilog and established verification methodologies.
• Create and maintain verification environments that support functional and coverage-driven verification.
• Develop directed and constrained-random test cases to validate design functionality and performance.
• Perform code and functional coverage analysis to assess verification completeness and design quality.
• Debug simulation failures, analyze verification results, and identify potential design issues.
• Collaborate with design engineers to understand design requirements and verify implementation accuracy.
• Support verification planning, documentation, and design review activities.
• Utilize scripting and automation techniques to improve verification efficiency and productivity.
• Contribute to mixed-signal verification activities, including simulation and behavioral modeling where applicable.
• Must-Have Skills SystemVerilog and Digital Verification: Knowledge of SystemVerilog and digital verification concepts, including test bench development and simulation-based verification.
• Verilog RTL Fundamentals: Understanding of RTL design principles and the ability to analyze and verify digital hardware designs.
• Verification Methodologies: Familiarity with coverage-driven verification concepts and structured verification practices.
• Scripting and Automation: Experience or coursework using scripting languages such as Python, Perl, or Tcl for automation and productivity improvements.
• Digital Interfaces and Protocols: Understanding of standard communication protocols such as I2C, SPI, UART, or similar interfaces.
• Problem Solving and Debugging: Ability to analyze simulation results, investigate failures, and resolve technical issues in a structured manner.
• Communication and Collaboration: Strong written and verbal communication skills with the ability to work effectively in a team environment.
• Preferred Education and Experience Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field. 0-2 years of experience in digital design verification or a related engineering discipline.
• New graduates with relevant academic projects, internships, or coursework in digital design, verification, or semiconductor engineering are encouraged to apply.
• Exposure to Universal Verification Methodology (UVM), constrained-random verification, or SystemVerilog Assertions (SVA) is a plus.
• Familiarity with EDA simulation and debugging tools is preferred.
• Exposure to mixed-signal simulation, analog behavioral modeling, or object-oriented programming concepts is beneficial.
• For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S.
• Department of Commerce - Bureau of Industry and Security and/or the U.S.
• Department of State - Directorate of Defense Trade Controls.
• As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
• We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
• EEO is the Law: Notice of Applicant Rights Under the Law .
• Job Req Type: Graduate Job Required Travel: Yes, 10% of the time