Senior Digital/AMS Validation and Integration Engineer
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What You'll Do
- RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers.
- Mixed-Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.
- Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains.
- Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon.
- Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware.
- Functional Correctness: Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.
- Skills & Qualifications Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.
- HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.
- Timing & Implementation: Strong understanding of Static Timing Analysis (STA) , clock domain crossing (CDC), and constraints (SDC).
- Scripting & Automation: Deep experience with Python or Perl for hardware control, test automation, and data processing.
- Lab Skills: Proficient in using logic analyzers, high-speed scopes, and JTAG/I2C/SPI protocols for on-chip debugging.
- Preferred Experience Experience with 10GBase-T, ASA, or Automotive Ethernet standards.
- Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE).
- Knowledge of DFT (Design for Test) and BIST (Built-In Self-Test) insertion for high-speed links.
- Able to create Verilog-A models The base salary range for this position is as mentioned below per year.
- We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
- Company benefits include health. dental, and vision insurance. 401(k), and paid leave.
- Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs.
- This base pay range is specific to California and is not applicable to other locations.
- A reasonable estimate of the base salary range as of the date of this posting is: $166,200 to $228,500 annually More information about NXP in the United States...
- NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
- In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692
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Salary range
₹4-10 LPA to ₹40-75 LPA
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Job ID
/job/San-Jose-Holger-Way/Senior-Digital-AMS-Validation-and-Integration-Engineer_R-10061645
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