PRINCIPAL PHYSICAL VERIFICATION ENGINEER

What You'll Do

• Perform physical verification (PV) for block-level and full-chip designs, including: Design Rule Check ( DRC ) Layout Versus Schematic ( LVS ) Electrical Rule Check ( ERC ) Antenna, density, and reliability checks Drive signoff closure by identifying and resolving PV violations efficiently.
• Work with physical design and layout teams to debug and fix violations.
• Develop and maintain runsets, decks, and automation flows using industry-standard tools.
• Analyze foundry decks and PDK updates , ensuring compliance with process requirements.
• Lead tapeout readiness reviews and ensure high-quality database delivery.
• Perform hierarchical verification and regression management .
• Participate in improving verification methodologies, runtime, and capacity optimization .
• Interface with foundry and EDA vendors to resolve tool or deck-related issues.
• Mentor junior engineers and review their work as needed.
• Preferred / Added Advantage Skills Exposure to Physical Design (PD) concepts, including: Floorplanning (macro placement, block shaping, congestion awareness) Power Delivery Network (PDN) design (power grid, IR drop considerations) Understanding of: Placement, CTS, routing flows PD-PV interaction and impact of layout decisions on DRC/LVS closure Knowledge of: EM/IR, latch-up, ESD reliability checks Multi-patterning / EUV constraints Experience with full-chip integration and SoC-level challenges Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots) Exposure to flow automation and methodology development Soft Skills Strong analytical and problem-solving ability Effective communication across cross-functional teams Ownership mindset with focus on quality and timelines Ability to work independently and guide team members More information about NXP in India... #LI-29f4